Description:
As an Application Engineer Manager in the System & Verification Group (SVG), you will be responsible for overseeing teams in the areas of:
Simulation Xcelium
Verification Methodologies: UVM, MDV, ABV
Regressions, Vmanager
Emulation on Palladium and prototyping with Protium
Jasper Formal
You will help Cadence customers effectively deploy our industry-leading verification products to the world's top Semiconductor and System companies.
You will manage a team of Field Application Engineers (FAE) to understand the customers' key concerns and provide guidance on the best technologies and methodologies to enable their success.
This role will focus on the industry management of a team in System Verification and will require you to ramp up on functional verification and system validation spaces, which are the fastest growing segments in the semiconductor design industry, being responsible for engagements.
You will provide technical support in the Pre and Post-Sales process and will work with the FAE and account team to come up with innovative solutions to address our customers' most challenging problems.
Key Responsibilities in this Position Are To:
Manage a team in the System Verification group reporting to higher management.
Engage and lead the AE team on Pre-sales technical campaigns from the technical side, working alongside Sales and Marketing.
Provide world-class proactive support, training, and problem consultation to make our users successful.
Conduct root cause analysis and provide resolution to customer technical issues.
Collaborate with R&D on: Simulation, Emulation, prototyping, and formal areas.
Help R&D and product engineers develop competitive and creative technical solutions.
Understand the competitive landscape and continuously work on differentiating Cadence's solutions.
Minimum Requirements:
BSE or graduation in related areas.
Track record of experience leading a technical team.
Excellent RTL understanding and coding.
6+ years of experience in functional verification.
Knowledge of Unix, C/C++.
A strong interest in contributing to customer success with related technical interest in EDA, HDL's, and Logic Design.
Excellent English written and oral communication skills.
Nice to Have Skills:
Design fundamentals such as architecture, micro-architecture, HDLs Synthesis, and timing.
Verification skills such as UVM testbench architecture, development, and debug, SystemVerilog, SVAF.
Fundamental SoC Architecture knowledge.
Embedded software development and HW/SW co-design and co-verification.
Some knowledge of formal verification technologies.
Scripting languages such as Perl, Python, TCL, Bash.
Additional Job Details:
Employment category: CLT
Employment term: 40 hours/week
Location: Avenida do Contorno, 5800 5th Floor, Savassi, Belo Horizonte, MG, Brazil
About Cadence Design Systems:
Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging, to boards, and to systems.
We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play.
Our products are used in mobile, consumer, cloud datacenters, automotive, aerospace, IoT, industrial, and other market segments.
For more information, access our website.
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