Lead Solutions Engineer: Analog Design - Implementation and VerificationAt Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Cadence Design Systems Inc. is seeking a motivated Lead Solutions Engineer: Analog Design - Implementation and Verification to join our team in Brazil.In this role, you will be part of the Silicon Engineering team, working alongside an experienced Cadence team and leading-edge customers to implement analog IPs and subsystems in advanced process nodes. You will be responsible for developing block-level specifications, modeling, design, layout and verification of high-speed analog circuits, using Cadence's market-leading technologies to help customers bring their design ideas into the market.Job Description:Review of industry standards (e.g., SerDes, UCIe, Ethernet) to develop analog sub-blocks from specification to final verification.Identify and refine analog circuit architectures to optimize power, area and performance targets.Propose design and verification strategies that efficiently use simulator features to ensure high-quality design.Oversee and implement physical layouts to minimize the effects of parasitics, device stress, and process variations.Present simulation data for peer and customer reviews.Document design features and test plans.Provide mentorship for less experienced team members.Requirements:Bachelor's or Master's degree in computer or electrical engineering, or a related field.In-depth knowledge of transistor-level circuit design and CMOS fundamentals.Design experience with and familiarity with the following analog sub-circuits: voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillators, delay-locked loops, phase-locked loops, regulators, bandgap references, ADCs, and DACs.Familiarity with custom digital design (e.g., high-speed critical paths).Strong understanding of high-speed layout considerations, such as parasitics, crosstalk isolation, and supply and bias distribution.Advanced proficiency in EDA tools for analog circuit design and verification, preferably using the Cadence Virtuoso environment, including simulation, parasitic extraction, electromagnetic modeling, EM/IR and reliability analysis, as well as LVS and DRC.Experience with Verilog-A for analog behavioral modeling and simulation control/data capture.Excellent problem-solving and communication skills, with the ability to work effectively in a team environment.Nice to have:Experience with advanced nodes layout.Scripting skills in Perl, Python, or SKILL are a plus.Additional Details:Employment category: CLTWork schedule: 40 hours/weekHybrid workCompetitive benefitsAbout Cadence:Cadence has been nominated as a Great Place to Work globally and in Brazil and is also a Fortune 100 Best Companies to Work For.Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. For more information, visit http://www.cadence.com.Be proud and passionate about the work you do. Together, our One Cadence – One Team culture drives our success.We're doing work that matters. Help us solve what others can't.
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