Principal Design Verification Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Cadence is seeking an experienced design verification engineer who will play a critical role in the development of custom accelerator SoCs, in partnership with Cadence computational simulation teams.The qualified candidate will closely work together with ARCH, RTL and FW/SW team in implementation and optimization of our accelerator solution. The candidate must possess hands-on experience and excellent debugging skills in developing System Verilog/UVM based testbenches. Ability to independently verify complex modules in the context of subsystem/SOC using systemic metric-driven approach must be demonstrated. Past participation in successful IP delivery or SOC tape-out is highly desired. Effective cross-team communication and documentation skill is strongly preferred. Experience in automating verification regression and/or management of revision control is a plus.Activities:ASIC/Processor Design Verification positionOwn all aspects of block/sub-system design-verification:Test-plan creation/executionTest-bench (all components) creation/enhancement/maintenanceCode/functional coverageWill be involved in post silicon validation/bring up/EmulationJob Requirements:Strong expertise in building test-benches using: System-Verilog, UVM, C/C++Strong digital logic fundamentals and understandingExperience in functional coverage/code coverage/assertions (SVA) development and closureExperience in creating and maintaining *executable* test plansStrong debug skillsProficient in scripting/automation using any standard scripting language like Perl etc.Emulation related experience will be a plusExcellent verbal and written communication skills and a good team playerWe're doing work that matters. Help us solve what others can't.